1. Technical Field
The present invention relates to a clock synchronization apparatus, and more particularly, to a clock synchronization apparatus capable of reducing to a minimum a delay difference between an external clock and an internal clock of a semiconductor memory apparatus.
2. Related Art
In general, in order to perform a high-speed operation, a semiconductor memory apparatus that operates in synchronization with an external clock includes a clock buffer that receives a clock signal from the outside of the semiconductor memory apparatus and converts the received clock signal into a clock necessary for the internal operation of a chip. The use of the clock buffer causes a difference between the phases of clock signals in the apparatuses of the chip receiving clock buffer output.
When an internal clock signal is delayed by a predetermined amount of time relative to an external clock signal, the high-frequency characteristics of the semiconductor memory apparatus deteriorates. In particular, the time required to output data after the external clock is supplied, that is, an output data access time tAC is lengthened, or an error occurs. Therefore, a circuit for accurately synchronizing the phase of the internal clock signal with the phase of the external clock signal is needed to improve the high-frequency characteristics of the semiconductor memory apparatus. A delay-locked loop (DLL) or a phase-locked loop (PLL) is generally used for this purpose.
Both the DLL and PLL include a replica delay unit. The DLL includes, for example, an input buffer which receives an external clock and outputs the external clock, a delay unit which receives the clock output from the input buffer and outputs an internal clock delayed by the control of a phase-detecting unit, a replica delay unit which delays the clock signal output from the delay unit according to the modeling result of the external clock along an actual path and outputs the delayed clock signal, and a phase-detecting unit which compares the phase of a signal output from the replica delay unit with the phase of a signal output from the input buffer.
However, since the path of the clock modeled by the replica delay unit differs from the actual path of the clock, it is difficult to accurately synchronize the external clock with the internal clock even though the replica delay unit is used.
Further, when the replica delay unit is used, a large number of delay elements should be additionally provided in the replica delay unit in order to correct the distorted output data access time tAC. In order to provide suitable delay elements, a test process and a correcting process should be performed, resulting in a long development time. In this case, the delay of the clock signal can be corrected through complicated processes, but it is difficult to solve the problem of the output data access time tAC being distorted, since the semiconductor memory apparatus is greatly affected by the external environment (process, voltage, temperature; PVT).